View M48T59Y-70MH1_2246125.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/29 november 2004 m48t59 m48t59y, m48t59v* 5.0 or 3.3v, 64 kbit (8 kbit x8) timekeeper ? sram * contact local st sales office for availability of 3.3v version. features summary integrated ultra low power sram, real time clock, power-fail control circuit, and battery frequency test output for real time clock software calibration automatic power-fail chip deselect and write protection write protect voltages (v pfd = power-fail deselect voltage): ? m48t59: v cc = 4.75 to 5.5v 4.5v v pfd 4.75v ? m48t59y: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v ? m48t59v*: v cc = 3.0 to 3.6v 2.7v v pfd 3.0v self-contained battery and crystal in the caphat? dip package packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat top which contains the battery and crystal microprocessor power-on reset (valid even during battery back-up mode) programmable alarm output active in the battery back-up mode battery low flag figure 1. 28-pin pcdip, caphat? package figure 2. 28-pin soic package 28 1 pcdip28 (pc) battery/crystal caphat 28 1 soh28 (mh) snaphat (sh) battery/crystal
m48t59, m48t59y, m48t59v* 2/29 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. 28-pin pcdip, caphat? package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. 28-pin soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. 28-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. pcdip28 caphat connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. write enable controlled, write mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 9. chip enable controlled, write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 calibrating the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10.crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11.clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12.alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. alarm repeat mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13.back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 programmable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 initial power-on defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v cc noise and negative going transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14.supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3/29 m48t59, m48t59y, m48t59v* maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15.ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16.power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17.pcdip28 ? 28-pin plastic dip, battery caphat, package outline . . . . . . . . . . . . . . . . 23 table 14. pcdip28 ? 28-pin plastic dip, battery caphat, package mechanical data. . . . . . . . . 23 figure 18.soh28 ? 28-lead plastic small outline, battery snaphat, package outline . . . . . . . . 24 table 15. soh28 ? 28-lead plastic small outline, battery snaphat, pack. mech. data . . . . . . . 24 figure 19.sh ? 4-pin snaphat housing for 48mah battery & crystal, package outline . . . . . . . 25 table 16. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mech. data. . . . 25 figure 20.sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline . . . . . . 26 table 17. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data. . . 26 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 table 19. snaphat battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
m48t59, m48t59y, m48t59v* 4/29 summary description the m48t59/y/v timekeeper ? ram is an 8 kb x8 non-volatile static ram and real time clock. the monolithic chip is available in two spe- cial packages to provide a highly integrated bat- tery backed-up memory and real time clock solution. the m48t59/y/v is a non-volatile pin and function equivalent to any jedec standard 8 kb x8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28-pin, 600mil dip caphat? houses the m48t59/y/v silicon with a quartz crystal and a long life lithium button cell in a single package. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. inser- tion of the snaphat housing after reflow pre- vents potential battery and crystal damage due to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the bat- tery/crystal package (e.g., snaphat) part num- ber is ?m4t28-br12sh? or ?m4t32-br12sh? (see table 19., page 27 ). caution: do not place the snaphat battery/crys- tal top in conductive foam, as this will drain the lith- ium button-cell battery. figure 3. logic diagram table 1. signal names ai01380e 13 a0-a12 w dq0-dq7 v cc m48t59 m48t59y m48t59v g v ss 8 e rst irq/ft a0-a12 address inputs dq0-dq7 data inputs / outputs irq /ft interrupt / frequency test output (open drain) rst reset output (open drain) e chip enable g output enable w write enable v cc supply voltage v ss ground
5/29 m48t59, m48t59y, m48t59v* figure 4. 28-pin soic connections figure 5. pcdip28 caphat connections figure 6. block diagram ai01382e 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 irq/ft a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 rst v cc m48t59y m48t59v a1 a0 dq0 a7 a4 a3 a2 a6 a5 irq/ft a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 rst v cc ai01381d m48t59 m48t59y 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 ai01383d lithium cell oscillator and clock chain v pfd rst v cc v ss 32,768 hz crystal voltage sense and switching circuitry 16 x 8 biport sram array 8176 x 8 sram array a0-a12 dq0-dq7 e w g power irq/ft
m48t59, m48t59y, m48t59v* 6/29 operation modes as figure 6., page 5 shows, the static memory ar- ray and the quartz-controlled clock oscillator of the m48t59/y/v are integrated on one silicon chip. the two circuits are interconnected at the upper eight memory locations to provide user accessible bytewide? clock information in the bytes with addresses 1ff8h-1fffh. the clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour bcd format (except for the century). corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. byte 1ff8h is the clock control reg- ister. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport? read/write memory cells. the m48t59/y/v includes a clock control cir- cuit which updates the clock bytes with current in- formation once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t59/y/v also has its own power-fail de- tect circuit. the control circuitry constantly moni- tors the single 5v/3.3v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpre- dictable system operation brought on by low v cc . as v cc falls below the battery back-up switchover voltage (v so ), the control circuitry connects the battery which maintains data and clock operation until valid power returns. table 2. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 13., page 22 for details. mode v cc e g w dq7-dq0 power deselect 4.75 to 5.5v or 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
7/29 m48t59, m48t59y, m48t59v* read mode the m48t59/y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the unique address specified by the 13 ad- dress inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be avail- able at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 7. read mode ac waveforms note: write enable (w ) = high. table 3. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v, 4.75 to 5.5v, or 3.0 to 3.6v (except where noted). 2. c l = 100pf (see figure 15., page 20 ). 3. c l = 5pf (see figure 15., page 20 ). symbol parameter (1) m48t59/y/v unit ?70 min max t avav read cycle time 70 ns t avqv (2) address valid to output valid 70 ns t elqv (2) chip enable low to output valid 70 ns t glqv (2) output enable low to output valid 35 ns t elqx (3) chip enable low to output transition 5 ns t glqx (3) output enable low to output transition 5 ns t ehqz (3) chip enable high to output hi-z 25 ns t ghqz (3) output enable high to output hi-z 25 ns t axqx (2) address transition to output transition 10 ns ai01385 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a12 e g dq0-dq7 valid
m48t59, m48t59y, m48t59v* 8/29 write mode the m48t59/y/v is in the write mode whenever w and e are low. the start of a write is refer- enced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of anoth- er read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; however, if the output bus has been activated by a low on e and g a low on w will disable the outputs t wlqz af- ter w falls. figure 8. write enable controlled, write mode ac waveforms figure 9. chip enable controlled, write mode ac waveforms ai01386 tavav twhax tdvwh data input a0-a12 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01387b tavav tehax tdveh a0-a12 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
9/29 m48t59, m48t59y, m48t59v* table 4. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v, 4.75 to 5.5v, or 3.0 to 3.6v (except where noted). 2. c l = 5pf (see figure 15., page 20 ). 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48t59/y/v unit ?70 min max t avav write cycle time 70 ns t avwl address valid to write enable low 0 ns t avel address valid to chip enable low 0 ns t wlwh write enable pulse width 50 ns t eleh chip enable low to chip enable high 55 ns t whax write enable high to address transition 0 ns t ehax chip enable high to address transition 0 ns t dvwh input valid to write enable high 30 ns t dveh input valid to chip enable high 30 ns t whdx write enable high to input transition 5 ns t ehdx chip enable high to input transition 5 ns t wlqz (2,3) write enable low to output hi-z 25 ns t av wh address valid to write enable high 60 ns t av eh address valid to chip enable high 60 ns t whqx (2,3) write enable high to output transition 5 ns
m48t59, m48t59y, m48t59v* 10/29 data retention mode with valid v cc applied, the m48t59/y/v operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high imped- ance, and all inputs are treated as ?don't care.? note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t59/y/v may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data and powers the clock. the internal button cell will maintain data in the m48t59/y/v for an accumulated period of at least 7 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is discon- nected and the power supply is switched to exter- nal v cc . deselect continues for t rec after v cc reaches v pfd (max). for more information on battery storage life refer to the application note an1012.
11/29 m48t59, m48t59y, m48t59v* clock operations reading the clock updates to the tim ekeeper ? registers should be halted before clock data is read to prevent reading data in transition. the biport? time- keeper cells in the ram array are only data reg- isters and not the actual clock counters, so updating the registers can be halted without dis- turbing the clock itself. updating is halted when a '1' is written to the read bit, d6 in the control register (1ff8h). as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0.' setting the clock bit d7 of the control register (1ff8h) is the write bit. setting the write bit to a '1,' like the read bit, halts updates to the time keeper reg- isters. the user can then load them with the cor- rect day, date, and time data in 24 hour bcd format (see table 5., page 12 ). resetting the write bit to a '0' then transfers the values of all time registers (1ff9h-1fffh) to the actual time- keeper counters and allows normal operation to resume. after the write bit is reset, the next clock update will occur within approximately one second. see the application note an923, ?tim ekeeper rolling into the 21st century? for information on century rollover. note: upon power-up following a power failure, both the write bit and the read bit will be reset to '0.' stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. setting it to a '1' stops the oscillator. the m48t59/y/v in the dip package is shipped from stmicroelectronics with the stop bit set to a '1.' when reset to a '0,' the m48t59/y/v oscillator starts within one sec- ond. note: it is not necessary to set the write bit when setting or resetting the frequency test bit (ft), the stop bit (st) or the century en- able bit (ceb).
m48t59, m48t59y, m48t59v* 12/29 table 5. register map keys: s = sign bit ft = frequency test bit r = read bit w = write bit st = stop bit 0 = must be set to '0' y = '1' or '0' z = '0' and are read only af = alarm flag (read only) bl = battery low (read only) wds = watchdog steering bit bmb0-bmb4 = watchdog multiplier bits rb0-rb1 = watchdog resolution bits afe = alarm flag enable abe = alarm in battery back-up mode enable rpt1-rpt4 = alarm repeat mode bits wdf = watchdog flag (read only) ceb = century enable bit cb = century bit address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 1fffh 10 years year year 00-99 1ffeh 0 0 0 10 m month month 01-12 1ffdh 0 0 10 date date date 01-31 1ffch 0 ft ceb cb 0 day century/day 00-01/01-07 1ffbh 0 0 10 hours hours hours 00-23 1ffah 0 10 minutes minutes minutes 00-59 1ff9h st 10 seconds seconds seconds 00-59 1ff8h w r s calibration control 1ff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 1ff6hafeyabeyyyyyinterrupts 1ff5h rpt4 y al. 10 date alarm date alarm date 01-31 1ff4h rpt3 y al. 10 hours alarm hours alarm hours 00-23 1ff3h rpt2 alarm 10 minutes alarm minutes alarm minutes 00-59 1ff2h rpt1 alarm 10 seconds alarm seconds alarm seconds 00-59 1ff1hyyyyyyyy unused 1ff0h wdf af z bl z z z z flags
13/29 m48t59, m48t59y, m48t59v* calibrating the clock the m48t59/y/v is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m48t59/y/v improves to better than +1/?2 ppm at 25c. the oscillation rate of any crystal changes with temperature (see figure 10., page 14 ). most clock chips compensate for crystal frequency and tem- perature shift error with cumbersome ?trim? capac- itors. the m48t59/y/v design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in fig- ure 11., page 14 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register (1ff8h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is the sign bit; '1' in- dicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 osc illator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtract ing 256 oscillator cycles; for every 125,829,120 actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t59/y/v may re- quire. the first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the fi- nal product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq/ ft pin. the pin will toggle at 512 hz when the stop bit (d7 of 1ff9h) is '0,' the ft bit (d6 of 1ffch) is '1,' the afe bit (d7 of 1ff6h) is '0,' and the watchdog steering bit (d7 of 1ff7h) is '1' or the watchdog register is reset (1ff7h = 0). any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a ?10 (wr001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. the irq /ft pin is an open drain output which re- quires a pull-up resistor for proper operation. a 500-10k ? resistor is recommended in order to control the rise time. the ft bit is cleared on pow- er-down. for more information on calibration, see applica- tion note an934, ?timeke eper calibration.?
m48t59, m48t59y, m48t59v* 14/29 figure 10. crystal accuracy across temperature figure 11. clock calibration ai00999 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 ? f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ai00594b normal positive calibration negative calibration
15/29 m48t59, m48t59y, m48t59v* setting the alarm clock registers 1ff5h-1ff2h contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific day of the month or repeat every month, day, hour, minute, or second. it can also be programmed to go off while the m48t59/y/v is in the battery back-up mode of op- eration to serve as a system wake-up call. bits rpt1-rpt4 put the alarm in the repeat mode of operation. table 6., page 15 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. note: user must transition address (or toggle chip enable) to see flag bit change. when the clock information matches the alarm clock settings based on the match criteria defined by rpt1-rpt4, af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condi- tion activates the irq /ft pin. to disable the alarm, write '0' to the alarm date register and rpt1-4. the alarm flag and the irq /ft output are cleared by a read to the flags register as shown in figure 12., page 15 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /ft pin can also be activated in the bat- tery back-up mode. the irq /ft will go low if an alarm occurs and both the abe (alarm in battery back-up mode enable) and the afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot -up to determine if an alarm was generated while the m48t59/y/v was in the dese- lect mode during power-down. figure 13., page 16 illustrates the back-up mode alarm timing. figure 12. alarm interrupt reset waveform table 6. alarm repeat mode rpt4 rpt3 rpt2 rpt1 alarm activated 1111 once per second 1110 once per minute 1100 once per hour 1000 once per day 0000 once per month ai01388b 15ns min a0-a12 active flag bit irq/ft address 1ff0h high-z
m48t59, m48t59y, m48t59v* 16/29 figure 13. back-up mode alarm waveforms ai03254b v cc irq/ft trec v pfd (max) v pfd (min) abe, afe bit in interrupt register af bit in flags register high-z v so high-z
17/29 m48t59, m48t59y, m48t59v* watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the eight-bit watchdog register (ad- dress 1ff7h). the five bits (bmb4-bmb0) that store a binary multiplier and the two lower order bits (rb1-rb0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 sec- ond, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for ex- ample: writing 00001110 in the watchdog regis- ter = 3 x 1 or 3 seconds). note: accuracy of timer is within the selected resolution. if the processor does not reset the timer within the specified period, the m48t59/y/v sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. wdf is reset by reading the flags register (address 1ff0h). note: user must transition address (or toggle chip enable) to see flag bit change. the most significant bit of the watchdog register is the watchdog steering bit. when set to a '0,' the watchdog will activate the irq /ft pin when timed- out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for a dura- tion of t rec . the watchdog register, the ft bit, and the afe and abe bits will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer resets when the microproces- sor performs a re-write of the watchdog register. the time-out period then starts over. the watch- dog timer is disabled by writing a value of 00000000 to the eight bits in the watchdog regis- ter. the watchdog function is automatically disabled upon power-down and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. power-on reset the m48t59/y/v continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). rst is valid for all v cc conditions. the rst pin is an open drain output and an appropriate resistor to v cc should be chosen to control rise time. programmable interrupts the m48t59/y/v provides two programmable in- terrupts; an alarm and a watchdog. when an inter- rupt condition occurs, the m48t59/y/v sets the appropriate flag bit in the flag register 1ff0h. the interrupt enable bits in (afe and abe) in 1ff6h and the watchdog steering (wds) bit in 1ff7h allow the interrupt to activate the irq /ft pin. the alarm flag and the irq /ft output are cleared by a read to the flags register. an interrupt con- dition reset will not occur unless the addresses are stable at the flag location for at least 15ns while the device is in the read mode as shown in fig- ure 12., page 15 . the irq /ft pin is an open drain output and re- quires a pull-up resistor (10k ? recommended) to v cc . the pin remains in the high impedance state unless an interrupt occurs or the frequency test mode is enabled. battery low flag the m48t59/y/v automatically performs periodic battery voltage monitoring upon power-up and at factory-programmed time intervals of 24 hours (at day rollover) as long as the device is powered and the oscillator is running. the battery low flag (bl), bit d4 of the flags register 1ff0h, will be asserted high if the internal or snaphat ? battery is found to be less than approximately 2.5v. the bl flag will remain active until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that the battery voltage is below 2.5v (approximately), which may be insuffi- cient to maintain data integrity. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates the battery is near end of life. however, data has not been com- promised due to the fact that a nominal v cc is sup- plied. in order to insure data integrity during subsequent periods of battery back-up mode, it is recommended that the battery be replaced. the snaphat top may be replaced while v cc is ap- plied to the device. note: this will cause the clock to lose time during the interval the battery/crystal is removed. note: battery monitoring is a useful technique only when performed periodically. the m48t59/y/v only monitors the battery when a nominal v cc is applied to the device. thus applications which re- quire extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is in- dicated, data integrity should be verified upon power-up via a checksum or other technique.
m48t59, m48t59y, m48t59v* 18/29 century bit bit d5 and d4 of clock register 1ffch contain the century enable bit (ceb) and the cen- tury bit (cb). setting ceb to a '1' will cause cb to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. note : the write bit must be set in order to write to the century bit. initial power-on defaults upon application of power to the device, the fol- lowing register bits are set to a '0' state: wds; bmb0-bmb4; rb0-rb1; afe; abe; w; r; ft (see table 7. ). table 7. default values note: 1. wds, bmb0-bmb4, rbo, rb1. 2. state of other control bits undefined. 3. state of other control bits remains unchanged. 4. assuming these bits set to '1' prior to power-down. v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 14. ) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 14. supply voltage protection condition w r ft afe abe watchdog register (1) initial power-up (battery attach for snaphat) (2) 00000 0 subsequent power-up / reset (3) 00000 0 power-down (4) 00011 0 ai02169 v cc 0.1 f device v cc v ss
19/29 m48t59, m48t59y, m48t59v* maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 8. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package, standard (snpb) lead finish: reflow at peak temperature of 225c (total thermal budget not to exceed 180c fo r between 90 to 150 seconds). 3. for so package, lead-free (pb-free) lead finish: reflow at peak temperature of 260c (total thermal budget not to exceed 245 c for greater than 30 seconds). caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) ?40 to 85 c t sld (1,2,3) lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to 7 v v cc supply voltage m48t59/m48t59y ?0.3 to 7 v m48t59v ?0.3 to 4.6 i o output current 20 ma p d power dissipation 1 w
m48t59, m48t59y, m48t59v* 20/29 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 9. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 15. ac measurement load circuit note: excluding open-drain output pins 1. 50pf for m48t59v. table 10. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m48t59 m48t59y m48t59v unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0 to 70 0 to 70 0 to 70 c load capacitance (c l ) 100 100 50 pf input rise and fall times 5 5 5ns input pulse voltages 0 to 3 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 1.5 v ai02325 c l = 100pf (1) c l includes jig capacitance 645 ? device under test 1.75v symbol parameters (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
21/29 m48t59, m48t59y, m48t59v* table 11. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v, 4.75 to 5.5v, or 3.0 to 3.6v (except where noted). 2. outputs deselected. 3. negative spikes of ?1v allowed for up to 10ns once per cycle. 4. the irq /ft and rst pins are open drain. symbol parameter test condition (1) m48t59/y m48t59v unit min max min max i li input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i cc supply current outputs open 50 30 ma i cc1 supply current (standby) ttl e = v ih 32ma i cc2 supply current (standby) cmos e = v cc ? 0.2v 31ma v il (3) input low voltage ?0.3 0.8 ?0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v output low voltage (irq /ft and rst ) (4) i ol = 10ma 0.4 0.4 v v oh output high voltage i oh = ?1ma 2.4 2.4 v
m48t59, m48t59y, m48t59v* 22/29 figure 16. power down/up mode ac waveforms table 12. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v, 4.75 to 5.5v, or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. table 13. power down/up trip points dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v, 4.75 to 5.5v, or 3.0 to 3.6v (except where noted). 2. all voltages referenced to v ss . 3. at 25c, v cc = 0v. symbol parameter (1) min max unit t pd e or w at v ih before power down 0s t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec v pfd (max) to rst high 40 200 ms symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage m48t59 4.5 4.6 4.75 v m48t59y 4.2 4.35 4.5 v m48t59v 2.7 2.9 3.0 v v so battery back-up switchover voltage m48t59/y 3.0 v m48t59v v pfd ?100mv v t dr (3) expected data retention time 7 years ai03258 v cc inputs rst outputs don't care high-z tf tfb tr trec trb tdr valid valid v pfd (max) v pfd (min) v so tpd recognized recognized (per control input) (per control input)
23/29 m48t59, m48t59y, m48t59v* package mechanical information figure 17. pcdip28 ? 28-pin plastic dip, battery caphat, package outline note: drawing is not to scale. table 14. pcdip28 ? 28-pin plastic dip, battery caphat, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n 28 28 pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3
m48t59, m48t59y, m48t59v* 24/29 figure 18. soh28 ? 28-lead plastic small outline, battery snaphat, package outline note: drawing is not to scale. table 15. soh28 ? 28-lead plastic small outline, battery snaphat, pack. mech. data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e1.27? ?0.050? ? eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 0 8 0 8 n 28 28 cp 0.10 0.004 soh-a e n d c l a1 1 h a cp be a2 eb
25/29 m48t59, m48t59y, m48t59v* figure 19. sh ? 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 16. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mech. data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
m48t59, m48t59y, m48t59v* 26/29 figure 20. sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 17. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
27/29 m48t59, m48t59y, m48t59v* part numbering table 18. ordering information scheme note: 1. the m48t59 part is offered with the pcdip28 (e.g., caphat?) package only. 2. contact local st sales office for availability of 3.3v version. 3. the soic package (soh28) requires the snaphat ? battery/crystal package which is ordered separately under the part number ?m4txx-br12sh? in plastic tube or ?m4txx-br12shtr? in tape & reel form (see table 19 ). caution : do not place the snaphat battery package ?m4txx-br12sh? in conductive foam as it will drain the lithium button-cell bat- tery. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 19. snaphat battery table example: m48t 59y ?70 mh 1 e device type m48t supply voltage and write protect voltage 59 (1) = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 59y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 59v (2) = v cc = 3.0 to 3.6v; v pfd = 2.7 to 3.0v speed ?70 = 70ns package pc = pcdip28 mh (3) = soh28 temperature range 1 = 0 to 70c shipping method for soh28: blank = tubes (not for new design - use e) e = lead-free package (eco pack ? ), tubes f = lead-free package (eco pack ? ), tape & reel tr = tape & reel (not for new design - use f) for pcdip28: blank = tubes part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
m48t59, m48t59y, m48t59v* 28/29 revision history table 20. document revision history date version revision details october 1999 1.0 first issue 22-mar-00 1.1 century bit paragraph added; t fb value changed (table 12 ) 13-jul-00 2.0 from preliminary data to data sheet 14-may-01 3.0 reformatted, ind. temp. added (table 9 ), snaphat table added (table 19 ), temp/voltage info. added to tables (table 10 , 11 , 3 , 4 , 12 , 13 ) 31-jul-01 3.1 formatting changes from recent document review findings 06-aug-01 3.2 fix text for setting the alarm clock (figure 12 ) 20-may-02 3.3 modify reflow time and temperature footnotes (table 8 ) 07-aug-02 3.4 add marketing status note (table 18 ) 01-apr-03 4.0 v2.2 template applied; test condition updated (table 13 ) 02-apr-04 5.0 reformatted; update lead-free package information (table 8 , 18 ) 25-nov-04 6.0 remove all industrial temperature references (table 3 , 4 , 8 , 9 , 11 , 12 , 13 , 18 )
29/29 m48t59, m48t59y, m48t59v* information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of M48T59Y-70MH1

	To Download M48T59Y-70MH1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .